CλaSH

From Haskell to Hardware

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Example

FIR filter

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fir coeffs x = dotp coeffs (window x)
  where
    dotp as bs = sum (zipWith (*) as bs)
  Parametric in the number of filter taps
     
  Parametric in the data type
     
  Strongly-typed, yet free from type annotations
Why

Why use CλaSH

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circuits. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
  • Compile your designs for fast simulation.
  • Higher-order functions, in combination with type inference, result in designs that are fully parametric by default.
  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.
  • Multiple clock domains, with type safe clock domain crossing.
  • Template language for introducing new VHDL/(System)Verilog primitives.
setup details

How do I install CλaSH?

Please file a bug report if the following installation instructions do not work for you.

The CλaSH compiler is written in Haskell and is compiled from source using the the GHC Haskell compiler version 8.0 (earlier versions of GHC are not supported):

  1. Install GHC 8.0

    • Download GHC for your platform. Unix users can use ./configure --prefix=<LOCATION> to set the installation location
    • Make sure the bin directory of GHC is in your PATH

    In case you cannot find what you are looking for on https://www.haskell.org/ghc/download_ghc_8_0_2, you can, alternatively, use the following instructions:

    • Ubuntu:
      • sudo add-apt-repository -y ppa:hvr/ghc
      • sudo apt-get update
      • sudo apt-get install cabal-install-1.24 ghc-8.0.2 libtinfo-dev
      • update your PATH with: /opt/ghc/8.0.2/bin, /opt/cabal/1.24/bin and $HOME/.cabal/bin
      • Run `cabal update
      • Skip step 2.
    • OS X:
      • Follow the instructions on: Haskell Platform Mac OS X to install the minimal Haskell platform.
      • Run cabal update
      • Skip step 2.
    • Windows:
      • Follow the instructions on: Haskell Platform Windows to install the minimal Haskell platform
      • Run cabal update
      • Skip step 2.
  2. Install Cabal (version 1.24)

    • Binary, when available:
      • Download the binary for cabal-install
      • Put the binary in a location mentioned in your PATH
      • Add cabal’s bin directory to your PATH:
        • Windows: %appdata%\cabal\bin
        • Unix: $HOME/.cabal/bin
    • Source:
      • Download the sources for cabal-install
      • Unpack (tar xf) the archive and cd to the directory
      • Run sh bootstrap.sh
      • Follow the instructions to add cabal to your PATH
    • Run cabal update
  3. Install CλaSH

    • Run:
      • i386 Linux: cabal install clash-ghc --enable-documentation --enable-executable-dynamic
      • Other: cabal install clash-ghc --enable-documentation
      • If you get the error can't load .so/.DLL for: libtinfo.so (libtinfo.so: cannot open shared object file: No such file or directory), add a symlink from libtinfo.5.so to libtinfo.so, and retry the cabal install process.
    • This is going to take awhile, so have a refreshment xkcd
usage

Alright, you’ve got the compiler installed, now it’s time for some testing:

  • Download the FIR.hs example
  • Run clash --interactive FIR.hs
  • Execute, in the interpreter, the :vhdl command.
  • Execute, in the interpreter, the :verilog command.
  • Execute, in the interpreter, the :systemverilog command.
  • Exit the interpreter using :q
  • Examine the VHDL code in the vhdl directory
  • Examine the Verilog code in the verilog directory
  • Examine the SystemVerilog code in the systemverilog directory
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